1. Field of The Invention
This invention relates to an information processor employing an electronic computer.
2. Description of The Related Art
Referring first to FIG. 5, there is shown a conventional information processor. In this figure, reference numeral 101 represents an instruction decoding portion; 102 a register conflict detecting portion for detecting a phenomenon referred to as "register conflict" (to be described later) occurring between two registers respectively used by two instructions to consecutively be executed; 103 a register portion comprised of a plurality of registers including "0 register" which holds 32-bit data representing 0 (hereunder referred to as zero data); 104 an integer arithmetic portion which includes an arithmetic and logical unit (ALU); 105 a data transfer control portion for controlling transfer of data between the register portion 103 and data cache (not shown); 501 a data address generating portion for generating data addresses; 110 an instruction bus for transmitting instructions; 111 an immediate data bus for transmitting 32-bit immediate data; 112 a first internal data bus for transmitting 32-bit internal data; 113 a second internal data bus for transmitting 32-bit internal data; 114 a third internal data bus for transmitting 32-bit internal data; 115 a data address bus for transmitting 32-bit data addresses; 116 a store data bus for transferring 32-bit data to be stored in the data cache from the register portion 103 to the data cache; 117 a load data bus for transferring 32-bit data to be loaded from the data cache to the register portion 103; and 118 control signals sent from the instruction decoding portion 101 to the data address generating portion 501.
FIG. 6 is a schematic block diagram for showing internal structure of the data address generating portion 501 of the conventional information processor of FIG. 5. In FIG. 6, reference numerals 203 and 601 designate 32-bit multiplexers; 202 a 32-bit adder; and 204 a 32-bit feed back latch. Further, reference numerals 111, 112 and 113 denote the 32-bit immediate data bus, the 32-bit first internal data bus and the 32-bit second internal data bus illustrated in FIG. 5, respectively. Moreover, reference numeral 210 indicates a data bus for transferring 32-bit data outputted from the multiplexer 601 to the adder 202; and 211 an addition result output bus for transmitting an output of the adder 202. Furthermore, reference numeral 115 represents the data address bus illustrated in FIG. 5. Further, reference numeral 212 represents a held data bus for transmitting data which is outputted to the data address bus 115 one clock cycle ago and then is held by the feed back latch 204; 213 a data selection signal, which is a part of the control signals 118 of FIG. 5, indicating a selection condition to be used in the multiplexer 601; and 214 an address holding signal, which is also a part of the control signal 118 of FIG. 5, indicating a selection condition to be used in the multiplexer 203.
Hereinafter, an operation of the conventional information processor constructed as above described will be explained.
This conventional information processor is a pipeline consisting of four stages. Further, in this conventional information processor, an operation is effected on only data stored in two 32-bit registers. Then, the results of the operation is stored again in the register. Furthermore, in this conventional information processor, data is transferred from (or to) a memory only to (or from) the registers. Additionally, this conventional information processor employs "load and store" architecture.
FIG. 7 is a timing chart for illustrating a manner of processing operation instructions of this conventional information processor. In this figure, reference characters C1, C2 . . . represent processing cycles; and A and B operation instructions to be processed.
First, the manner of processing operation instructions in this conventional information processor will be described hereinbelow by referring to FIGS. 5 and 7.
In C1 Cycle, an operation instruction A is fetched and is sent to an instruction bus 110.
Further, in C2 Cycle, the operation instruction A sent to the instruction bus 110 is decoded by the instruction decoding portion 101. The instruction decoding portion 101 sends out a control signal 118 representing control information corresponding to the decoded instruction.
Then, the information processor performs the following two kinds of processing according to kinds of the operation instruction A.
(1) In case where the operation instruction A directs the information processor to perform an operation on data stored in two 32-bit registers, a register portion 103 sends out two kinds of data respectively stored in the two 32-bit registers, which are indicated by the control signal 118, to the first internal data bus 112 and the second internal data bus 113, respectively.
(2) On the other hand, in case where the operation instruction A directs the information processor to set immediate data indicated by the instruction A in a specific register, the instruction decoding portion 101 sends out the immediate data to the immediate data bus 111. Further, the register portion 103 sends out data 0 stored in the 32-bit "0 register" indicated by the control signal 118 to the first internal data bus 112. Moreover, an operation instruction B is fetched and is sent to the instruction bus 110.
Next, in C3 Cycle, the integer arithmetic portion 104 carries out an operation indicated by the control signal 118 which is issued by the instruction decoding portion 101 in C2 Cycle. At that time, there are two kinds of data, which respectively corresponding to the two cases
(1) and (2) in C2 Cycle, to be used in this operation.
(1) In case where the operation instruction A directs the information processor to perform an operation on data stored in the two 32-bit registers, data, which is sent from the register portion 103 to the first internal data 112 and the second internal data bus 113 in C2 Cycle, is inputted to the integer arithmetic portion 104 and performs an operation on the input data. After the operation is finished, results of the operation are sent to the 32-bit third internal data bus 114.
(2) In case where the operation instruction A directs the information processor to set immediate data indicated by the instruction A in the specific register, the immediate data sent by the instruction decoding portion 101 to the immediate data bus 111 is inputted to the integer arithmetic portion 104, and further performs an addition of the input data and 0 sent by the register portion 103. Upon completion of this operation, results of this operation is sent to the 32-bit third internal data bus 114.
Incidentally, the operation instruction B is processed in the same manner as in case of the operation instruction A in C2 Cycle. Thus, a detailed description of the processing of the operation instruction B is omitted.
Further, in C4 Cycle, the register portion 103 stores the data, which is sent by the integer arithmetic portion 104 to the third internal data bus 114, in the register indicated by the control signal 118 in C2 Cycle.
Incidentally, in this cycle, the operation instruction B is processed in the same manner as in case of the operation instruction A in C3 Cycle. Thus, a detailed description of the processing of the operation instruction B is omitted.
Next, the manner of processing an operation instruction, which requires calculation of addresses (hereunder sometimes referred to as memory addresses) of a memory, in this conventional information processor will be described hereinbelow. By way of example, the manner of processing a store instruction for storing data, which is held in a register, in a memory of the conventional information processor.
FIGS. 8 and 9 are timing charts for illustrating the manner of processing a store instruction for storing the data in the memory of the conventional information processor. Especially, FIG. 8 is a timing chart for the manner of processing store instruction in case where the store instruction (hereunder sometimes referred to as the "none-cycle store" instruction) directs a "one-cycle store" operation, namely, in case where data held in a 32-bit register is added to the immediate data indicated by the store instruction to calculate a memory address at which data should be stored. Further, FIG. 8 is a timing chart for illustrating the manner of processing store instruction in case where the store instruction (hereunder sometimes referred to as the "two-cycle store" instruction) directs a "two-cycle store" operation, namely, in case where data held in two 32-bit registers are added to the immediate data indicated by the store instruction to calculate a memory address at which data should be stored.
First, an "one-cycle store" operation of the conventional information processor will be described hereinafter by referring to FIGS. 5, 6 and 8. For simplicity of description, let "(r1)" denote data held in a register to be used for address calculation at the tune of effecting "one-cycle store" operation; "(immA)" immediate data; and "(r2)" data to be stored in the memory, i.e., the data cache.
In C1 Cycle, the store instruction A is fetched and is further sent to the instruction bus 110.
Further, in C2 Cycle, the store instruction A sent to the instruction bus 110 is decoded by the instruction decoding portion 101. Then, the instruction decoding portion 101 sends out the control signal 118 representing control information and also sends out the immediate data (immA) to the immediate data bus 111. Moreover, the register portion 103 sends out the data (r1) stored in the 32-bit register, which is indicated by the control signal 118 and is used for calculation of memory addresses, to the second internal data bus 113 and also sends out data (r2) held in the 32-bit register, which should be stored in the memory, to the first internal data bus 112.
Next, an operation of the data address generating portion 501 will be described hereinbelow. The multiplexer 601 outputs the immediate data (immA) of the immediate data bus 111 to the data bus 210 in accordance with information represented by the data selection signal 213 which is sent out as the control signal 118. The adder 202 adds the immediate data (immA), which is outputted to the 32-bit data bus 210, and the data (r1), which is outputted to the second internal data bus 113. Further, the adder 202 outputs results of the addition to the addition result output bus 211. The multiplexer 203 outputs the data transmitted on the addition result output bus 211 to the data address bus 115 according to information represented by the address holding signal 214 which is outputted as the control signal 118. Thus, address {(immA)+(r1)} at which data should be stored is sent out to the data address bus 115.
In C3 Cycle, the data cache is accessed by using the address {(immA)+(r1)} sent out to the data address bus 115. Here, it is assumed that the data cache is hit. Further, the data transfer control portion 105 latches the data (r2) outputted to the first internal data bus 112.
Furthermore, in C4 Cycle, the data transfer control portion 105 outputs the data (r2) latched in C3 Cycle to the store data bus 116 and the data (r2) is stored in the cache.
Next, a "two-cycle store" operation of the conventional information processor will be described hereinafter by referring to FIGS. 5, 6 and 9. For simplicity of description, let "(r1)" and "(r2)" denote data held in registers to be used for address calculation at the time of effecting "two-cycle store" operation; and "(r3)" data, which is held in the register, to be stored in the memory, i.e., the data cache.
In C1 Cycle, the store instruction A is fetched and is further sent to the instruction bus 110.
Further, in C2 Cycle, the store instruction A sent to the instruction bus 110 is decoded by the instruction decoding portion 101. Then, the instruction decoding portion 101 sends out the control signal 118 representing control information. Moreover, the register portion 103 sends out the data (r1) and the data (r2) stored in the two 32-bit registers, which are indicated by the control signal 118 and is used for calculation of memory addresses, to the first internal data bus 112 and the second internal data bus 113, respectively.
Next, an operation of the data address generating portion 501 will be described hereinbelow. The multiplexer 601 outputs the data transmitted on the first internal data bus 112 to the data bus 210 in accordance with information represented by the data selection signal 213 which is sent out as the control signal 118. The adder 202 adds the data (r1), which is outputted to the data bus 210, and the data (r2), which is outputted to the second internal data bus 113. Further, the adder 202 outputs results of the addition to the addition result output bus 211. The multiplexer 203 outputs the data transmitted on the addition result output bus 211 to the data address bus 115 according to the information represented by the address holding signal 214 which is outputted as the control signal 118. Thus, address {(r1)+(r2)} at which data should be stored is sent out to the data address bus 115.
In C3 Cycle, the instruction decoding portion 101 outputs a control signal 118 which represents control information indicating a second cycle of the "two-cycle store" operation on the basis of the fact that the store instruction A decoded in C2 Cycle directs a "two-cycle store" operation.
Subsequently, the register portion 103 sends out the data (r3), which is held in the 32-bit register indicated by the control signal 118, to the first internal data bus 112. To keep outputting results of the addition effected in C3 Cycle to the data address bus 115 in accordance with information represented by the address holding signal 214, which is sent out as the control signal 118, the data address generating portion 501 controls the multiplexer 203 in such a manner that the data {(r1)+(r2)} transmitted on the holding data bus 212 is outputted to the data address bus 115. Further, the instruction decoding portion 101 does not decode the next instruction (see "nop" in FIG. 9) because the instruction decoded in C2 Cycle directs a "two-cycle store" operation.
Further, in C4 Cycle, the data cache is accessed by using the address {(r1)+(r2)} sent out to the data address bus 115. Here, it is assumed that the data cache is hit. Furthermore, the data transfer control portion 105 latches the data (r3) outputted to the first internal data bus 112.
Thereafter, in C5 Cycle, the data transfer control portion 105 outputs the data (r3) latched in C4 Cycle to the store data bus 116 and the data (r3) is stored in the cache.
As described above, a "two-cycle store" instruction requires data held in three registers. Thus, five cycles are needed for execution of the "two-cycle store" instruction. As a result, each time a "two-cycle store" instruction is executed, the pipeline is put into an idle state for a period of one cycle.
Next, will be described hereinbelow an operation of the conventional information processor in case where an operation instruction for setting immediate data in a specific register and another instruction requiring calculation of memory addresses are succeedingly effected and moreover a register used for the calculation of memory addresses for execution of the latter instruction is in agreement with a register in which the immediate data is set by the former operation instruction (namely, a register conflict occurs).
Here, a store instruction is cited as an example of the instruction requiring calculation of memory addresses.
FIGS. 10 and 11 are timing charts for illustrating an operation of the conventional information processor in case where an operation instruction A for setting immediate data in a specific register and a store instruction B are succeedingly effected and moreover a register used for the calculation of memory addresses for execution of the latter store instruction B is in agreement with a register in which the immediate data is set by the former operation instruction A (namely, a register conflict occurs). Especially, FIG. 10 is a timing chart for illustrating an operation in case where the store instruction B is a "one-cycle store" instruction. FIG. 11 is a timing chart for illustrating an operation in case where the store instruction B is a "two-cycle store" instruction.
By referring to FIGS. 5, 6 and 10, an operation of the conventional information processor in case where the operation instruction A for setting immediate data in a specific register and a "one-cycle store" instruction B are succeedingly effected and moreover a conflict between a register used for the calculation of memory addresses for execution of the store instruction B and a register, in which the immediate data should be set by the former operation instruction A, occurs. For simplicity of description, let "r1" denote the register coming into conflict with the register in which the immediate data should be set; "(immA)" the immediate data set by the operation instruction A; "(immB)" the immediate data to be used for calculation of addresses required by the "one-cycle store" instruction B; and "(r2)" data, which is held in the register, to be stored in the memory, i.e., the data cache.
In C1 Cycle, (1) the processing of the operation instruction A is as follows. Namely, the operation instruction A is fetched and further is sent to the instruction bus 110.
Then, in C2 Cycle, (1) the processing of the operation instruction A is as follows. Namely, the operation instruction A sent out to the instruction bus 110 is decoded by the instruction decoding portion 101. The instruction decoding portion 101 sends out the control signal 118 representing control information to the data address generating portion 501 and further outputs the immediate data (immA) to the immediate data bus 111. Moreover, the register portion 103 sends out data, which is held in the 32-bit "0 register" indicated by the control signal 118, to the first internal data bus 112.
On the other hand, (2) the processing of the store instruction B is as follows. Namely, the store instruction B is fetched and is then sent out to the instruction bus 110.
Next, in C3 Cycle, (1) the processing of the operation instruction A is as follows. Namely, the immediate data (immA), which is sent out by the instruction decoding portion 101 to the immediate data bus 111, is inputted to the integer arithmetic portion 104. Further, the integer arithmetic portion 104 performs an addition of this input data and 0 sent out by the register portion 103 to the first internal data bus 112. Upon completion of this addition, the integer arithmetic portion 104 outputs results of the addition to the 32-bit third internal data bus 114.
On the other hand, (2) the processing of the store instruction B is as follows. That is, the store instruction B sent to the instruction bus 110 is first decoded by the instruction decoding portion 101. Then, the instruction decoding portion 101 outputs the control signal 118 to the data address generating portion 501 and also outputs immediate data (immB) to the immediate data bus 111. Further, the register portion 103 sends out the data (r1), which is used for calculation of memory addresses and is held in the 32-bit register indicated by the control signal 118, to the second internal data bus 113 and also sends out the data (r2), which should be stored in a memory and is held in the 32-bit register, to the first internal data bus 112. Incidentally, the data (r1) transmitted on the second internal data bus 113 is invalid data because the execution of the operation instruction A is not completed. The register conflict detecting portion 102 performs detection of a register conflict between the register r1 used for calculation of memory addresses required for execution of the store instruction B and the register r1, in which the immediate data should be set, for the operation instruction A, which precedes the instruction B, in parallel with the above described processing of the instruction decoding portion 101. Further, the register conflict detecting portion 102 informs the instruction decoding portion 101 of results of the detection.
Furthermore, in C4 Cycle, (1) the processing of the operation instruction A is as follows. The immediate data (immA) sent out by the integer arithmetic portion 104 in C3 Cycle to the third internal data bus 114 is stored in the register r1 indicated by the control signal 118 in C2 Cycle.
Additionally, (2) the processing of the store instruction B is as follows. As the result of the fact that the register conflict detecting portion 102 detects a conflict between the register r1 used for the execution of the store instruction B and the register r1 in C3 Cycle, the instruction decoding portion 101 continues decoding the store instruction B similarly as in C3 Cycle and further sends out the control signal 118 representing control information and moreover sends out the immediate data (immB) to the immediate data bus 111. The register portion 103 sends out the data (r1), which is held in the 32-bit register used for the calculation of the memory addresses, to the second internal data bus 113 and sends out the data (r2), which should be stored in the memory and is held in the 32-bit register, to the first internal data bus 112.
Next, an operation of the data address generating portion 501 will be described.
First, the multiplexer 601 outputs the immediate data (immB) transmitted on the immediate data bus 111 to the data bus 210 in accordance with the information represented by the data selection signal 213 which is outputted as the control signal 118. The adder 202 adds the immediate data (immB) and the data (r1) respectively outputted to the 32-bit data bus 210 and the second internal data bus 113 and outputs results of the addition to the addition result output bus 211. Then, the multiplexer 203 outputs the data transmitted on the addition result output bus 211 to the data address bus 115 in accordance with information represented by the address holding signal 214 which is sent out as the control signal 18. Thus, an address {(immB)+(r1)} at which the data should be stored is sent out to the data address bus 115.
Incidentally, operations of C5 and C6 Cycles are similar to operations of C3 and C4 Cycles which are above described regarding the "one-cycle store" operation. Therefore, description of the operations of C5 and C6 Cycles is omitted (see the description of FIG. 8).
As described above, in case where a register conflict between the register r1 used for calculation of memory addresses required for execution of the "one-cycle store" instruction B and the register r1, in which the immediate data should be set for execution of the operation instruction A, the pipeline is put into an idle state for a period of one cycle. In the foregoing description, a "one-cycle store" instruction is cited as an example of an instruction requiring calculation of memory addresses. However, in case where a register conflict occurs when another load instruction or branch instruction requiring calculation of memory addresses is executed, the pipeline is also put into an idle state for a period of one cycle.
Similarly, in case where a register conflict between the register used for calculation of memory addresses required for execution of the "two-cycle store" instruction B and the register, in which the immediate data should be set for execution of the operation instruction A, the pipeline is put into an idle state for a period of two cycles. An operation of the information processor in this case is similar to the operation of the case of the "one-cycle store" instruction B except for a point that the term "one-cycle store" should be replaced with the term "two-cycle store". Thus, detailed description of the operation of the information processor in this case is omitted. For a reference, a timing chart illustrating the operation of the information processor in this case is shown in FIG. 11.
Consequently, the conventional information processor having the above described arrangement has drawbacks that the pipeline is put into an idle state for a period of one cycle in case where a register conflict between the register r1 used for calculation of memory addresses required for execution of the "one-cycle store" instruction B and the register r1, in which the immediate data should be set for execution of the operation instruction A and that the pipeline is put into an idle state for a period of two cycles in case where a register conflict between the register used for calculation of memory addresses required for execution of the "two-cycle store" instruction B and the register, in which the immediate data should be set for execution of the operation instruction A. The present invention is created to eliminate the drawbacks of the conventional information processor.
It is accordingly an object of the present invention to provide an information processor which can eliminate an idle state of the pipeline and effect data processing at a high speed.